Conventional LOCOS isolation process will suffer from bird's beak enroachment and local field oxide thinning effect for deep sub-.mu.m technology as mentioned in the reference "A. Bryant, et al., in IEDM, p679,1994". By 1980, LOCOS was the standard MOSFET isolation technology. However, the scalability of LOCOS for sub-half-micron CMOS technologies was a question. The issues were the lateral extent of the LOCOS bird's beak, non-planarity, thinning, and the stress-induced silicon defects. Over a decade later, as we prepare for the 0.25 .mu.m 256 Mb DRAM generation and beyond, the CMOS isolation technology becomes critical. Insulator thinning at narrow dimensions, bird's beak formation, and field-implant encroachment are the key challenge to LOCOS scaling. Insulator thinning contributes to non uniform global planarity and reduced isolation depth. Post etch-back the bird's beak encroachment and field-implant boron encroachment into active regions degrade conduction at MOSFET edges. The result is narrow channel effect (NCE) that increases MOSFET thresholds.
Conventional shallow trench isolation process can solve the above problems, however, the plasma etching induced substrate damages and poor planarization are new issues. These problems has been discussed in references "A. Bryant, et al., in IEDM, p679,1994" and "J. Y. Cheng et al., J. of Electrochem., vol. 144,p.315,1997". As mentioned in the reference "J. Y. Cheng et al., J. of Electrochem., vol. 144,p.315,1997", the LOCOS-based isolation process results in a large encroachment of field oxide (bird's beak) into the devices' active regions, narrow width effect due to high-temperature oxidation, field oxide thinning effect, and nonplanar surface topology. The oxide-filled trench isolation technology is the most promising candidate to circumvent these problems. However, the conventional resist planarization and reactive ion etching (RIE) etchback process has cumulative tolerances associate with large film thickness and easily results in nonplanar surface topography.